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292 lines
9.9 KiB
292 lines
9.9 KiB
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_vref.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.vref"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address
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*
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* @param base VREF peripheral base address
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*
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* @return The VREF instance
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*/
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static uint32_t VREF_GetInstance(VREF_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to VREF bases for each instance. */
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static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to VREF clocks for each instance. */
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static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t VREF_GetInstance(VREF_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++)
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{
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if (s_vrefBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_vrefBases));
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return instance;
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}
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/*!
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* brief Enables the clock gate and configures the VREF module according to the configuration structure.
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*
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* This function must be called before calling all other VREF driver functions,
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* read/write registers, and configurations with user-defined settings.
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* The example below shows how to set up vref_config_t parameters and
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* how to call the VREF_Init function by passing in these parameters.
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* This is an example.
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* code
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* vref_config_t vrefConfig;
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* vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer;
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* vrefConfig.enableExternalVoltRef = false;
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* vrefConfig.enableLowRef = false;
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* VREF_Init(VREF, &vrefConfig);
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* endcode
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*
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* param base VREF peripheral address.
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* param config Pointer to the configuration structure.
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*/
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void VREF_Init(VREF_Type *base, const vref_config_t *config)
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{
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assert(config != NULL);
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uint8_t reg = 0U;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate clock for VREF */
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CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Configure VREF to a known state */
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#if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC
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/* Set chop oscillator bit */
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base->TRM |= VREF_TRM_CHOPEN_MASK;
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#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */
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/* Get current SC register */
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#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
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reg = base->VREFH_SC;
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#else
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reg = base->SC;
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#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
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/* Clear old buffer mode selection bits */
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reg &= ~(uint8_t)VREF_SC_MODE_LV_MASK;
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/* Set buffer Mode selection and Regulator enable bit */
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reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U);
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#if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION
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/* Set second order curvature compensation enable bit */
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reg |= VREF_SC_ICOMPEN(1U);
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#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */
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/* Enable VREF module */
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reg |= VREF_SC_VREFEN(1U);
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/* Update bit-field from value to Status and Control register */
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#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
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base->VREFH_SC = reg;
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#else
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base->SC = reg;
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#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
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#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
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reg = base->VREFL_TRM;
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/* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits */
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reg &= (uint8_t)(~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK));
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/* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */
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reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef);
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base->VREFL_TRM = reg;
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#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
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#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
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reg = base->TRM4;
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/* Clear old select internal voltage reference bit (2.1V) */
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reg &= ~(uint8_t)VREF_TRM4_VREF2V1_EN_MASK;
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/* Select internal voltage reference (2.1V) */
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reg |= VREF_TRM4_VREF2V1_EN(config->enable2V1VoltRef);
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base->TRM4 = reg;
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#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
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/* Wait until internal voltage stable */
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#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
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while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0U)
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#else
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while ((base->SC & VREF_SC_VREFST_MASK) == 0U)
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#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
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{
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}
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}
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/*!
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* brief Stops and disables the clock for the VREF module.
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*
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* This function should be called to shut down the module.
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* This is an example.
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* code
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* vref_config_t vrefUserConfig;
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* VREF_Init(VREF);
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* VREF_GetDefaultConfig(&vrefUserConfig);
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* ...
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* VREF_Deinit(VREF);
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* endcode
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*
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* param base VREF peripheral address.
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*/
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void VREF_Deinit(VREF_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate clock for VREF */
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CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Initializes the VREF configuration structure.
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*
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* This function initializes the VREF configuration structure to default values.
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* This is an example.
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* code
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* vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer;
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* vrefConfig->enableExternalVoltRef = false;
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* vrefConfig->enableLowRef = false;
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* endcode
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*
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* param config Pointer to the initialization structure.
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*/
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void VREF_GetDefaultConfig(vref_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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/* Set High power buffer mode in */
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#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
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config->bufferMode = kVREF_ModeHighPowerBuffer;
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#else
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config->bufferMode = kVREF_ModeTightRegulationBuffer;
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#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
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#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
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/* Select internal voltage reference */
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config->enableExternalVoltRef = false;
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/* Set VREFL (0.4 V) reference buffer disable */
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config->enableLowRef = false;
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#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
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#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
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/* Disable internal voltage reference (2.1V) */
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config->enable2V1VoltRef = false;
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#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
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}
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/*!
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* brief Sets a TRIM value for the reference voltage.
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*
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* This function sets a TRIM value for the reference voltage.
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* Note that the TRIM value maximum is 0x3F.
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*
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* param base VREF peripheral address.
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* param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
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*/
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void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue)
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{
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uint8_t reg = 0U;
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/* Set TRIM bits value in voltage reference */
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reg = base->TRM;
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reg = (uint8_t)((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue));
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base->TRM = reg;
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/* Wait until internal voltage stable */
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#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
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while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0U)
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#else
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while ((base->SC & VREF_SC_VREFST_MASK) == 0U)
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#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
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{
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}
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}
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#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
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/*!
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* brief Sets a TRIM value for the reference voltage (2V1).
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*
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* This function sets a TRIM value for the reference voltage (2V1).
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* Note that the TRIM value maximum is 0x3F.
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*
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* param base VREF peripheral address.
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* param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
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*/
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void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue)
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{
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uint8_t reg = 0U;
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/* Set TRIM bits value in voltage reference (2V1) */
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reg = base->TRM4;
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reg = (uint8_t)((reg & ~VREF_TRM4_TRIM2V1_MASK) | VREF_TRM4_TRIM2V1(trimValue));
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base->TRM4 = reg;
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/* Wait until internal voltage stable */
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while ((base->SC & VREF_SC_VREFST_MASK) == 0U)
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{
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}
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}
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#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
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#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
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/*!
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* brief Sets the TRIM value for the low voltage reference.
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*
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* This function sets the TRIM value for low reference voltage.
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* Note the following.
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* - The TRIM value maximum is 0x05U
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* - The values 111b and 110b are not valid/allowed.
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*
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* param base VREF peripheral address.
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* param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)).
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*/
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void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue)
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{
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/* The values 111b and 110b are NOT valid/allowed */
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assert((trimValue != 0x7U) && (trimValue != 0x6U));
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uint8_t reg = 0U;
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/* Set TRIM bits value in low voltage reference */
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reg = base->VREFL_TRM;
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reg = ((reg & (uint8_t)(~VREF_VREFL_TRM_VREFL_TRIM_MASK)) | VREF_VREFL_TRM_VREFL_TRIM(trimValue));
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base->VREFL_TRM = reg;
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/* Wait until internal voltage stable */
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while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0U)
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{
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}
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}
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#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
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