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1531 lines
62 KiB
1531 lines
62 KiB
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_dspi_edma.h"
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/***********************************************************************************************************************
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* Definitions
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***********************************************************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.dspi_edma"
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#endif
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/*!
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* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private.
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*/
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typedef struct _dspi_master_edma_private_handle
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{
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SPI_Type *base; /*!< DSPI peripheral base address. */
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dspi_master_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */
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} dspi_master_edma_private_handle_t;
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/*!
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* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private.
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*/
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typedef struct _dspi_slave_edma_private_handle
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{
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SPI_Type *base; /*!< DSPI peripheral base address. */
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dspi_slave_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */
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} dspi_slave_edma_private_handle_t;
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/***********************************************************************************************************************
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* Prototypes
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***********************************************************************************************************************/
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/*!
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* @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA.
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* This is not a public API.
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*/
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static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
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void *g_dspiEdmaPrivateHandle,
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bool transferDone,
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uint32_t tcds);
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/*!
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* @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA.
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* This is not a public API.
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*/
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static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
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void *g_dspiEdmaPrivateHandle,
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bool transferDone,
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uint32_t tcds);
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/***********************************************************************************************************************
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* Variables
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***********************************************************************************************************************/
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/*! @brief Pointers to dspi edma handles for each instance. */
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static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
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static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
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/***********************************************************************************************************************
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* Code
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***********************************************************************************************************************/
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/*!
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* brief Initializes the DSPI master eDMA handle.
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*
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* This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs. Usually, for a
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* specified DSPI instance, call this API once to get the initialized handle.
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*
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* Note that DSPI eDMA has separated (RX and TX as two sources) or shared (RX and TX are the same source) DMA request
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* source.
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* (1) For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
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* TX DMAMUX source for edmaIntermediaryToTxRegHandle.
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* (2) For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
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*
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* param base DSPI peripheral base address.
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* param handle DSPI handle pointer to dspi_master_edma_handle_t.
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* param callback DSPI callback.
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* param userData A callback function parameter.
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* param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
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* param edmaTxDataToIntermediaryHandle edmaTxDataToIntermediaryHandle pointer to edma_handle_t.
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* param edmaIntermediaryToTxRegHandle edmaIntermediaryToTxRegHandle pointer to edma_handle_t.
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*/
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void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base,
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dspi_master_edma_handle_t *handle,
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dspi_master_edma_transfer_callback_t callback,
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void *userData,
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edma_handle_t *edmaRxRegToRxDataHandle,
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edma_handle_t *edmaTxDataToIntermediaryHandle,
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edma_handle_t *edmaIntermediaryToTxRegHandle)
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{
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assert(NULL != handle);
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assert(NULL != edmaRxRegToRxDataHandle);
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#if (!(defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET))
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assert(NULL != edmaTxDataToIntermediaryHandle);
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#endif
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assert(NULL != edmaIntermediaryToTxRegHandle);
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/* Zero the handle. */
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(void)memset(handle, 0, sizeof(*handle));
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uint32_t instance = DSPI_GetInstance(base);
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s_dspiMasterEdmaPrivateHandle[instance].base = base;
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s_dspiMasterEdmaPrivateHandle[instance].handle = handle;
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handle->callback = callback;
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handle->userData = userData;
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handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle;
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handle->edmaTxDataToIntermediaryHandle = edmaTxDataToIntermediaryHandle;
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handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle;
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}
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/*!
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* brief DSPI master transfer data using eDMA.
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*
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* This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
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* is transferred, the callback function is called.
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*
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* note The max transfer size of each transfer depends on whether the instance's Tx/Rx shares the same DMA request. If
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* FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) is true, then the max transfer size is 32767 datawidth of data,
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* otherwise is 511.
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*
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* param base DSPI peripheral base address.
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* param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
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* param transfer A pointer to the dspi_transfer_t structure.
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* return status of status_t.
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*/
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status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer)
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{
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assert(NULL != handle);
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assert(NULL != transfer);
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/* If the transfer count is zero, then return immediately.*/
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if (transfer->dataSize == 0U)
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{
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return kStatus_InvalidArgument;
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}
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/* If both send buffer and receive buffer is null */
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if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData)))
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{
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return kStatus_InvalidArgument;
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}
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/* Check that we're not busy.*/
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if (handle->state == (uint8_t)kDSPI_Busy)
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{
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return kStatus_DSPI_Busy;
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}
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handle->state = (uint8_t)kDSPI_Busy;
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uint32_t instance = DSPI_GetInstance(base);
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uint16_t wordToSend = 0;
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uint8_t dummyData = DSPI_GetDummyDataInstance(base);
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uint8_t dataAlreadyFed = 0;
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uint8_t dataFedMax = 2;
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uint32_t tmpMCR = 0;
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size_t tmpRemainingSendByteCount = 0;
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uint32_t rxAddr = DSPI_GetRxRegisterAddress(base);
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uint32_t txAddr = DSPI_MasterGetTxRegisterAddress(base);
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edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU));
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edma_transfer_config_t transferConfigA = {0};
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edma_transfer_config_t transferConfigB = {0};
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handle->txBuffIfNull = ((uint32_t)dummyData << 8U) | dummyData;
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dspi_command_data_config_t commandStruct;
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DSPI_StopTransfer(base);
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DSPI_FlushFifo(base, true, true);
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DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag);
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commandStruct.whichPcs =
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(uint8_t)((uint32_t)1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT));
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commandStruct.isEndOfQueue = false;
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commandStruct.clearTransferCount = false;
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commandStruct.whichCtar = (uint8_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT);
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commandStruct.isPcsContinuous =
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(0U != (transfer->configFlags & (uint32_t)kDSPI_MasterPcsContinuous)) ? true : false;
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handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct));
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commandStruct.isEndOfQueue = true;
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commandStruct.isPcsContinuous =
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(0U != (transfer->configFlags & (uint32_t)kDSPI_MasterActiveAfterTransfer)) ? true : false;
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handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
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handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1U;
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tmpMCR = base->MCR;
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if ((0U != (tmpMCR & SPI_MCR_DIS_RXF_MASK)) || (0U != (tmpMCR & SPI_MCR_DIS_TXF_MASK)))
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{
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handle->fifoSize = 1U;
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}
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else
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{
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handle->fifoSize = (uint8_t)FSL_FEATURE_DSPI_FIFO_SIZEn(base);
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}
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handle->txData = transfer->txData;
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handle->rxData = transfer->rxData;
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handle->remainingSendByteCount = transfer->dataSize;
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handle->remainingReceiveByteCount = transfer->dataSize;
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handle->totalByteCount = transfer->dataSize;
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/* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
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* due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
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*/
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if (transfer->dataSize > DSPI_EDMA_MAX_TRANSFER_SIZE(base, (handle->bitsPerFrame)))
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{
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handle->state = (uint8_t)kDSPI_Idle;
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return kStatus_DSPI_OutOfRange;
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}
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/*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
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if ((0U != (transfer->dataSize & 0x1U)) && (handle->bitsPerFrame > 8U))
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{
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handle->state = (uint8_t)kDSPI_Idle;
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return kStatus_InvalidArgument;
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}
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DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
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EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback,
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&s_dspiMasterEdmaPrivateHandle[instance]);
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/*
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(1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
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channel_A minor link to channel_B , channel_B minor link to channel_C.
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Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer.
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channel_A:SPI_POPR to rxData,
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channel_B:next txData to handle->command (low 16 bits),
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channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data
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(handle->lastCommand to SPI_PUSHR).
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(2)For DSPI instances with separate RX and TX DMA requests:
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Rx DMA request -> channel_A
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Tx DMA request -> channel_C -> channel_B .
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channel_C major link to channel_B.
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So need prepare the first data in "intermediary" before the DMA
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transfer and then channel_B is used to prepare the next data to "intermediary"
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channel_A:SPI_POPR to rxData,
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channel_C: handle->command (32 bits) to SPI_PUSHR,
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channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data
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(handle->lastCommand to handle->Command).
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*/
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/*If dspi has separate dma request , prepare the first data in "intermediary" .
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else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/
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if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
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{
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/* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to
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* trigger the TX DMA channel and RX DMA request to trigger the RX DMA channel
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*/
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/*Prepare the firt data*/
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if (handle->bitsPerFrame > 8U)
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{
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/* If it's the last word */
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if (handle->remainingSendByteCount <= 2U)
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{
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if (NULL != handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData; /* increment to next data byte */
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wordToSend |= (uint16_t)(*(handle->txData)) << 8U;
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}
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else
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{
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wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData);
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}
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handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
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handle->command = handle->lastCommand;
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}
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else /* For all words except the last word , frame > 8bits */
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{
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if (NULL != handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData; /* increment to next data byte */
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wordToSend |= (uint16_t)(*(handle->txData)) << 8U;
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++handle->txData; /* increment to next data byte */
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}
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else
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{
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wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData);
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}
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handle->command = (handle->command & 0xffff0000U) | wordToSend;
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}
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}
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else /* Optimized for bits/frame less than or equal to one byte. */
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{
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if (NULL != handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData; /* increment to next data word*/
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}
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else
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{
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wordToSend = dummyData;
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}
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if (handle->remainingSendByteCount == 1U)
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{
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handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
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handle->command = handle->lastCommand;
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}
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else
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{
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handle->command = (handle->command & 0xffff0000U) | wordToSend;
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}
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}
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}
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else /*dspi has shared dma request*/
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{
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/* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
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* trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
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*/
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/* If bits/frame is greater than one byte */
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if (handle->bitsPerFrame > 8U)
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{
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while ((uint32_t)kDSPI_TxFifoFillRequestFlag ==
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(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag))
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{
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if (handle->remainingSendByteCount <= 2U)
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{
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if (NULL != handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData;
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wordToSend |= (uint16_t)(*(handle->txData)) << 8U;
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}
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else
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{
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wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData);
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}
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handle->remainingSendByteCount = 0;
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base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend;
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}
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/* For all words except the last word */
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else
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{
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if (NULL != handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData;
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wordToSend |= (uint16_t)(*(handle->txData)) << 8U;
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++handle->txData;
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}
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else
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{
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wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData);
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}
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handle->remainingSendByteCount -= 2U;
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base->PUSHR = (handle->command & 0xffff0000U) | wordToSend;
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}
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/* Try to clear the TFFF; if the TX FIFO is full this will clear */
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DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag);
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dataAlreadyFed += 2U;
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/* exit loop if send count is zero, else update local variables for next loop */
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if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == (dataFedMax * 2U)))
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{
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break;
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}
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} /* End of TX FIFO fill while loop */
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}
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else /* Optimized for bits/frame less than or equal to one byte. */
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{
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while ((uint32_t)kDSPI_TxFifoFillRequestFlag ==
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(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag))
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{
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if (NULL != handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData;
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}
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else
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{
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wordToSend = dummyData;
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}
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if (handle->remainingSendByteCount == 1U)
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{
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base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend;
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}
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else
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{
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base->PUSHR = (handle->command & 0xffff0000U) | wordToSend;
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}
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/* Try to clear the TFFF; if the TX FIFO is full this will clear */
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DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag);
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--handle->remainingSendByteCount;
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dataAlreadyFed++;
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/* exit loop if send count is zero, else update local variables for next loop */
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if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == dataFedMax))
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{
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break;
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}
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} /* End of TX FIFO fill while loop */
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}
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}
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/***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/
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EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
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transferConfigA.srcAddr = (uint32_t)rxAddr;
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transferConfigA.srcOffset = 0;
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if (NULL != handle->rxData)
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{
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transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]);
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transferConfigA.destOffset = 1;
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}
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else
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{
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transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull);
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transferConfigA.destOffset = 0;
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}
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transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes;
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if (handle->bitsPerFrame <= 8U)
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{
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transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes;
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transferConfigA.minorLoopBytes = 1;
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transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount;
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}
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else
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{
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transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes;
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transferConfigA.minorLoopBytes = 2;
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transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2U;
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}
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/* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
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handle->nbytes = (uint8_t)(transferConfigA.minorLoopBytes);
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EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
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(const edma_transfer_config_t *)(uint32_t)&transferConfigA, NULL);
|
|
EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
(uint32_t)kEDMA_MajorInterruptEnable);
|
|
|
|
if (handle->remainingSendByteCount == 0U)
|
|
{
|
|
EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
|
|
DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable);
|
|
DSPI_StartTransfer(base);
|
|
return kStatus_Success;
|
|
}
|
|
|
|
tmpRemainingSendByteCount = handle->remainingSendByteCount;
|
|
/*Calculate the last data : handle->lastCommand*/
|
|
if (((tmpRemainingSendByteCount > 0U) && (1U != (uint8_t)FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
|
|
((((tmpRemainingSendByteCount > 1U) && (handle->bitsPerFrame <= 8U)) ||
|
|
((tmpRemainingSendByteCount > 2U) && (handle->bitsPerFrame > 8U))) &&
|
|
(1U == (uint8_t)FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))))
|
|
{
|
|
if (NULL != handle->txData)
|
|
{
|
|
uint32_t bufferIndex = 0;
|
|
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
bufferIndex = handle->remainingSendByteCount - 1U;
|
|
}
|
|
else
|
|
{
|
|
bufferIndex = handle->remainingSendByteCount - 2U;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
bufferIndex = handle->remainingSendByteCount;
|
|
}
|
|
|
|
uint32_t tmpLastCommand = handle->lastCommand;
|
|
uint8_t *tmpTxData = handle->txData;
|
|
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
tmpLastCommand = (tmpLastCommand & 0xffff0000U) | tmpTxData[bufferIndex - 1U];
|
|
}
|
|
else
|
|
{
|
|
tmpLastCommand = (tmpLastCommand & 0xffff0000U) | ((uint32_t)tmpTxData[bufferIndex - 1U] << 8U) |
|
|
tmpTxData[bufferIndex - 2U];
|
|
}
|
|
|
|
handle->lastCommand = tmpLastCommand;
|
|
}
|
|
else
|
|
{
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
wordToSend = dummyData;
|
|
}
|
|
else
|
|
{
|
|
wordToSend = (((uint16_t)dummyData << 8U) | (uint16_t)dummyData);
|
|
}
|
|
handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
|
|
}
|
|
}
|
|
|
|
/* The feature of GASKET is that the SPI supports 8-bit or 16-bit writes to the PUSH TX FIFO,
|
|
* allowing a single write to the command word followed by multiple writes to the transmit word.
|
|
* The TX FIFO will save the last command word written, and convert a 8-bit/16-bit write to the
|
|
* transmit word into a 32-bit write that pushes both the command word and transmit word into
|
|
* the TX FIFO (PUSH TX FIFO Register In Master Mode)
|
|
* So, if this feature is supported, we can use use one channel to carry the receive data from
|
|
* receive regsiter to user data buffer, use the other channel to carry the data from user data buffer
|
|
* to transmit register,and use the scatter/gather function to prepare the last data.
|
|
* That is to say, if GASKET feature is supported, we can use only two channels for tansferring data.
|
|
*/
|
|
#if defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET
|
|
/* For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
|
|
* (handle->lastCommand) to PUSHR register.
|
|
*/
|
|
|
|
EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
|
|
|
|
if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) ||
|
|
((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))))
|
|
{
|
|
transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
|
|
transferConfigB.destAddr = (uint32_t)txAddr;
|
|
transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigB.srcOffset = 0;
|
|
transferConfigB.destOffset = 0;
|
|
transferConfigB.minorLoopBytes = 4;
|
|
transferConfigB.majorLoopCounts = 1;
|
|
|
|
EDMA_TcdReset(softwareTCD);
|
|
EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL);
|
|
}
|
|
|
|
/*User_Send_Buffer(txData) to PUSHR register. */
|
|
if (((handle->remainingSendByteCount > 2U) && (handle->bitsPerFrame <= 8U)) ||
|
|
((handle->remainingSendByteCount > 4U) && (handle->bitsPerFrame > 8U)))
|
|
{
|
|
if (handle->txData)
|
|
{
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
/* For DSPI with separate RX and TX DMA requests, one frame data has been carry
|
|
* to handle->command, so need to reduce the pointer of txData.
|
|
*/
|
|
transferConfigB.srcAddr =
|
|
(uint32_t)((uint8_t *)(handle->txData) - ((handle->bitsPerFrame <= 8U) ? (1U) : (2U)));
|
|
transferConfigB.srcOffset = 1;
|
|
}
|
|
else
|
|
{
|
|
/* For DSPI with shared RX and TX DMA requests, one or two frame data have been carry
|
|
* to PUSHR register, so no need to change the pointer of txData.
|
|
*/
|
|
transferConfigB.srcAddr = (uint32_t)((uint8_t *)(handle->txData));
|
|
transferConfigB.srcOffset = 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
|
|
transferConfigB.srcOffset = 0;
|
|
}
|
|
|
|
transferConfigB.destAddr = (uint32_t)txAddr;
|
|
transferConfigB.destOffset = 0;
|
|
|
|
transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
|
|
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
|
|
transferConfigB.minorLoopBytes = 1;
|
|
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1U;
|
|
}
|
|
else
|
|
{
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
|
|
transferConfigB.minorLoopBytes = 2;
|
|
transferConfigB.majorLoopCounts = (handle->remainingSendByteCount / 2U) - 1U;
|
|
}
|
|
|
|
EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, softwareTCD);
|
|
}
|
|
/* If only one word to transmit, only carry the lastcommand. */
|
|
else
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, NULL);
|
|
}
|
|
|
|
/*Start the EDMA channel_A , channel_C. */
|
|
EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
|
|
EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle);
|
|
|
|
/* Set the channel link.
|
|
* For DSPI instances with shared TX and RX DMA requests, setup channel minor link, first receive data from the
|
|
* receive register, and then carry transmit data to PUSHER register.
|
|
* For DSPI instance with separate TX and RX DMA requests, there is no need to set up channel link.
|
|
*/
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
/*Set channel priority*/
|
|
uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
|
|
uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel;
|
|
uint8_t t = 0;
|
|
|
|
if (channelPriorityLow > channelPriorityHigh)
|
|
{
|
|
t = channelPriorityLow;
|
|
channelPriorityLow = channelPriorityHigh;
|
|
channelPriorityHigh = t;
|
|
}
|
|
|
|
edma_channel_Preemption_config_t preemption_config_t;
|
|
preemption_config_t.enableChannelPreemption = true;
|
|
preemption_config_t.enablePreemptAbility = true;
|
|
preemption_config_t.channelPriority = channelPriorityLow;
|
|
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t);
|
|
/*if there is Rx DMA request , carry the 32bits data (handle->command) to user data first , then link to
|
|
channelC to carry the next data to PUSHER register.(txData to PUSHER) */
|
|
if (handle->remainingSendByteCount > 0U)
|
|
{
|
|
EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
kEDMA_MinorLink, handle->edmaIntermediaryToTxRegHandle->channel);
|
|
}
|
|
}
|
|
|
|
DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
|
|
|
|
/* Setup control info to PUSHER register. */
|
|
*((uint16_t *)&(base->PUSHR) + 1) = (handle->command >> 16U);
|
|
#else
|
|
|
|
/***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
|
|
write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
|
|
SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
|
|
|
|
EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
|
|
|
|
/*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
|
|
* (handle->lastCommand) to handle->Command*/
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
|
|
transferConfigB.destAddr = (uint32_t) & (handle->command);
|
|
transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigB.srcOffset = 0;
|
|
transferConfigB.destOffset = 0;
|
|
transferConfigB.minorLoopBytes = 4;
|
|
transferConfigB.majorLoopCounts = 1;
|
|
|
|
EDMA_TcdReset(softwareTCD);
|
|
EDMA_TcdSetTransferConfig(softwareTCD, (const edma_transfer_config_t *)(uint32_t)&transferConfigB, NULL);
|
|
}
|
|
|
|
tmpRemainingSendByteCount = handle->remainingSendByteCount;
|
|
/*User_Send_Buffer(txData) to intermediary(handle->command)*/
|
|
if (((((tmpRemainingSendByteCount > 2U) && (handle->bitsPerFrame <= 8U)) ||
|
|
((tmpRemainingSendByteCount > 4U) && (handle->bitsPerFrame > 8U))) &&
|
|
(1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
|
|
(1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
|
|
{
|
|
if (NULL != handle->txData)
|
|
{
|
|
transferConfigB.srcAddr = (uint32_t)(handle->txData);
|
|
transferConfigB.srcOffset = 1;
|
|
}
|
|
else
|
|
{
|
|
transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
|
|
transferConfigB.srcOffset = 0;
|
|
}
|
|
|
|
transferConfigB.destAddr = (uint32_t)(&handle->command);
|
|
transferConfigB.destOffset = 0;
|
|
|
|
transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
|
|
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
|
|
transferConfigB.minorLoopBytes = 1;
|
|
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2U;
|
|
}
|
|
else
|
|
{
|
|
/*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
|
|
majorlink , the majorlink would not trigger the channel_C*/
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1U;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
|
|
transferConfigB.minorLoopBytes = 2;
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2U - 2U;
|
|
}
|
|
else
|
|
{
|
|
/*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
|
|
* majorlink*/
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2U + 1U;
|
|
}
|
|
}
|
|
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel,
|
|
(const edma_transfer_config_t *)(uint32_t)&transferConfigB, softwareTCD);
|
|
EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, false);
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel,
|
|
(const edma_transfer_config_t *)(uint32_t)&transferConfigB, NULL);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel,
|
|
(const edma_transfer_config_t *)(uint32_t)&transferConfigB, NULL);
|
|
}
|
|
|
|
/***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
|
|
handle the last data */
|
|
|
|
edma_transfer_config_t transferConfigC = {0};
|
|
|
|
EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
|
|
|
|
tmpRemainingSendByteCount = handle->remainingSendByteCount;
|
|
/*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data
|
|
* (handle->lastCommand) to SPI_PUSHR*/
|
|
if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (tmpRemainingSendByteCount > 0U)))
|
|
{
|
|
transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand);
|
|
transferConfigC.destAddr = (uint32_t)txAddr;
|
|
transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigC.srcOffset = 0;
|
|
transferConfigC.destOffset = 0;
|
|
transferConfigC.minorLoopBytes = 4;
|
|
transferConfigC.majorLoopCounts = 1;
|
|
|
|
EDMA_TcdReset(softwareTCD);
|
|
EDMA_TcdSetTransferConfig(softwareTCD, (const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL);
|
|
}
|
|
|
|
tmpRemainingSendByteCount = handle->remainingSendByteCount;
|
|
if (((tmpRemainingSendByteCount > 1U) && (handle->bitsPerFrame <= 8U)) ||
|
|
((tmpRemainingSendByteCount > 2U) && (handle->bitsPerFrame > 8U)) ||
|
|
(1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
|
|
{
|
|
transferConfigC.srcAddr = (uint32_t)(&(handle->command));
|
|
transferConfigC.destAddr = (uint32_t)txAddr;
|
|
|
|
transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigC.srcOffset = 0;
|
|
transferConfigC.destOffset = 0;
|
|
transferConfigC.minorLoopBytes = 4;
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1U;
|
|
}
|
|
else
|
|
{
|
|
transferConfigC.majorLoopCounts = (handle->remainingSendByteCount / 2U) - 1U;
|
|
}
|
|
|
|
EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel,
|
|
(const edma_transfer_config_t *)(uint32_t)&transferConfigC, softwareTCD);
|
|
}
|
|
else
|
|
{
|
|
transferConfigC.majorLoopCounts = 1;
|
|
|
|
EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel,
|
|
(const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL);
|
|
}
|
|
|
|
EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, false);
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel,
|
|
(const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL);
|
|
}
|
|
|
|
/*Start the EDMA channel_A , channel_B , channel_C transfer*/
|
|
EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
|
|
EDMA_StartTransfer(handle->edmaTxDataToIntermediaryHandle);
|
|
EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle);
|
|
|
|
/*Set channel priority*/
|
|
uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
|
|
uint8_t channelPriorityMid = handle->edmaTxDataToIntermediaryHandle->channel;
|
|
uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel;
|
|
uint8_t t = 0;
|
|
if (channelPriorityLow > channelPriorityMid)
|
|
{
|
|
t = channelPriorityLow;
|
|
channelPriorityLow = channelPriorityMid;
|
|
channelPriorityMid = t;
|
|
}
|
|
|
|
if (channelPriorityLow > channelPriorityHigh)
|
|
{
|
|
t = channelPriorityLow;
|
|
channelPriorityLow = channelPriorityHigh;
|
|
channelPriorityHigh = t;
|
|
}
|
|
|
|
if (channelPriorityMid > channelPriorityHigh)
|
|
{
|
|
t = channelPriorityMid;
|
|
channelPriorityMid = channelPriorityHigh;
|
|
channelPriorityHigh = t;
|
|
}
|
|
edma_channel_Preemption_config_t preemption_config_t;
|
|
preemption_config_t.enableChannelPreemption = true;
|
|
preemption_config_t.enablePreemptAbility = true;
|
|
preemption_config_t.channelPriority = channelPriorityLow;
|
|
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityMid;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityMid;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
}
|
|
|
|
/*Set the channel link.*/
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
/*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB
|
|
to prepare the next 32bits data (txData to handle->command) */
|
|
if (handle->remainingSendByteCount > 1U)
|
|
{
|
|
EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink,
|
|
handle->edmaTxDataToIntermediaryHandle->channel);
|
|
}
|
|
|
|
DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
|
|
}
|
|
else
|
|
{
|
|
if (handle->remainingSendByteCount > 0U)
|
|
{
|
|
EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel);
|
|
|
|
EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink,
|
|
handle->edmaIntermediaryToTxRegHandle->channel);
|
|
}
|
|
|
|
DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable);
|
|
}
|
|
#endif
|
|
DSPI_StartTransfer(base);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Transfers a block of data using a eDMA method.
|
|
*
|
|
* This function transfers data using eDNA, the transfer mechanism is half-duplex. This is a non-blocking function,
|
|
* which returns right away. When all data is transferred, the callback function is called.
|
|
*
|
|
* param base DSPI base pointer
|
|
* param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
|
|
* param transfer A pointer to the dspi_half_duplex_transfer_t structure.
|
|
* return status of status_t.
|
|
*/
|
|
status_t DSPI_MasterHalfDuplexTransferEDMA(SPI_Type *base,
|
|
dspi_master_edma_handle_t *handle,
|
|
dspi_half_duplex_transfer_t *xfer)
|
|
{
|
|
assert(NULL != xfer);
|
|
assert(NULL != handle);
|
|
dspi_transfer_t tempXfer = {0};
|
|
status_t status;
|
|
|
|
if (true == xfer->isTransmitFirst)
|
|
{
|
|
tempXfer.txData = xfer->txData;
|
|
tempXfer.rxData = NULL;
|
|
tempXfer.dataSize = xfer->txDataSize;
|
|
}
|
|
else
|
|
{
|
|
tempXfer.txData = NULL;
|
|
tempXfer.rxData = xfer->rxData;
|
|
tempXfer.dataSize = xfer->rxDataSize;
|
|
}
|
|
/* If the pcs pin keep assert between transmit and receive. */
|
|
if (true == xfer->isPcsAssertInTransfer)
|
|
{
|
|
tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kDSPI_MasterActiveAfterTransfer;
|
|
}
|
|
else
|
|
{
|
|
tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kDSPI_MasterActiveAfterTransfer);
|
|
}
|
|
|
|
status = DSPI_MasterTransferBlocking(base, &tempXfer);
|
|
if (status != kStatus_Success)
|
|
{
|
|
return status;
|
|
}
|
|
|
|
if (true == xfer->isTransmitFirst)
|
|
{
|
|
tempXfer.txData = NULL;
|
|
tempXfer.rxData = xfer->rxData;
|
|
tempXfer.dataSize = xfer->rxDataSize;
|
|
}
|
|
else
|
|
{
|
|
tempXfer.txData = xfer->txData;
|
|
tempXfer.rxData = NULL;
|
|
tempXfer.dataSize = xfer->txDataSize;
|
|
}
|
|
tempXfer.configFlags = xfer->configFlags;
|
|
|
|
status = DSPI_MasterTransferEDMA(base, handle, &tempXfer);
|
|
|
|
return status;
|
|
}
|
|
static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
|
|
void *g_dspiEdmaPrivateHandle,
|
|
bool transferDone,
|
|
uint32_t tcds)
|
|
{
|
|
assert(NULL != edmaHandle);
|
|
assert(NULL != g_dspiEdmaPrivateHandle);
|
|
|
|
dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle;
|
|
|
|
dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
|
|
|
|
DSPI_DisableDMA((dspiEdmaPrivateHandle->base), (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
|
|
|
|
dspiEdmaPrivateHandle->handle->state = (uint8_t)kDSPI_Idle;
|
|
|
|
if (NULL != dspiEdmaPrivateHandle->handle->callback)
|
|
{
|
|
dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
|
|
kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief DSPI master aborts a transfer which is using eDMA.
|
|
*
|
|
* This function aborts a transfer which is using eDMA.
|
|
*
|
|
* param base DSPI peripheral base address.
|
|
* param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
|
|
*/
|
|
void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle)
|
|
{
|
|
assert(NULL != handle);
|
|
|
|
DSPI_StopTransfer(base);
|
|
|
|
DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
|
|
|
|
EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle);
|
|
EDMA_AbortTransfer(handle->edmaTxDataToIntermediaryHandle);
|
|
EDMA_AbortTransfer(handle->edmaIntermediaryToTxRegHandle);
|
|
|
|
handle->state = (uint8_t)kDSPI_Idle;
|
|
}
|
|
|
|
/*!
|
|
* brief Gets the master eDMA transfer count.
|
|
*
|
|
* This function gets the master eDMA transfer count.
|
|
*
|
|
* param base DSPI peripheral base address.
|
|
* param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
|
|
* param count A number of bytes transferred by the non-blocking transaction.
|
|
* return status of status_t.
|
|
*/
|
|
status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count)
|
|
{
|
|
assert(NULL != handle);
|
|
|
|
if (NULL == count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Catch when there is not an active transfer. */
|
|
if (handle->state != (uint8_t)kDSPI_Busy)
|
|
{
|
|
*count = 0;
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
size_t bytes;
|
|
|
|
bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base,
|
|
handle->edmaRxRegToRxDataHandle->channel);
|
|
|
|
*count = handle->totalByteCount - bytes;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Initializes the DSPI slave eDMA handle.
|
|
*
|
|
* This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs. Usually, for a
|
|
* specified DSPI instance, call this API once to get the initialized handle.
|
|
*
|
|
* Note that DSPI eDMA has separated (RN and TX in 2 sources) or shared (RX and TX are the same source) DMA request
|
|
* source.
|
|
* (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
|
|
* TX DMAMUX source for edmaTxDataToTxRegHandle.
|
|
* (2)For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
|
|
*
|
|
* param base DSPI peripheral base address.
|
|
* param handle DSPI handle pointer to dspi_slave_edma_handle_t.
|
|
* param callback DSPI callback.
|
|
* param userData A callback function parameter.
|
|
* param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
|
|
* param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t.
|
|
*/
|
|
void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base,
|
|
dspi_slave_edma_handle_t *handle,
|
|
dspi_slave_edma_transfer_callback_t callback,
|
|
void *userData,
|
|
edma_handle_t *edmaRxRegToRxDataHandle,
|
|
edma_handle_t *edmaTxDataToTxRegHandle)
|
|
{
|
|
assert(NULL != handle);
|
|
assert(NULL != edmaRxRegToRxDataHandle);
|
|
assert(NULL != edmaTxDataToTxRegHandle);
|
|
|
|
/* Zero the handle. */
|
|
(void)memset(handle, 0, sizeof(*handle));
|
|
|
|
uint32_t instance = DSPI_GetInstance(base);
|
|
|
|
s_dspiSlaveEdmaPrivateHandle[instance].base = base;
|
|
s_dspiSlaveEdmaPrivateHandle[instance].handle = handle;
|
|
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle;
|
|
handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle;
|
|
}
|
|
|
|
/*!
|
|
* brief DSPI slave transfer data using eDMA.
|
|
*
|
|
* This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
|
|
* is transferred, the callback function is called.
|
|
* Note that the slave eDMA transfer doesn't support transfer_size is 1 when the bitsPerFrame is greater
|
|
* than eight.
|
|
*
|
|
* note The max transfer size of each transfer depends on whether the instance's Tx/Rx shares the same DMA request. If
|
|
* FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) is true, then the max transfer size is 32767 datawidth of data,
|
|
* otherwise is 511.
|
|
*
|
|
* param base DSPI peripheral base address.
|
|
* param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
|
|
* param transfer A pointer to the dspi_transfer_t structure.
|
|
* return status of status_t.
|
|
*/
|
|
status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer)
|
|
{
|
|
assert(NULL != handle);
|
|
assert(NULL != transfer);
|
|
|
|
/* If send/receive length is zero */
|
|
if (transfer->dataSize == 0U)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* If both send buffer and receive buffer is null */
|
|
if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData)))
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Check that we're not busy.*/
|
|
if (handle->state == (uint8_t)kDSPI_Busy)
|
|
{
|
|
return kStatus_DSPI_Busy;
|
|
}
|
|
|
|
handle->state = (uint8_t)kDSPI_Busy;
|
|
|
|
uint32_t instance = DSPI_GetInstance(base);
|
|
uint8_t whichCtar = (uint8_t)((transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT);
|
|
handle->bitsPerFrame =
|
|
(((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1U;
|
|
|
|
/* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
|
|
* due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
|
|
*/
|
|
if (transfer->dataSize > DSPI_EDMA_MAX_TRANSFER_SIZE(base, (handle->bitsPerFrame)))
|
|
{
|
|
handle->state = (uint8_t)kDSPI_Idle;
|
|
return kStatus_DSPI_OutOfRange;
|
|
}
|
|
|
|
/*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
|
|
if ((0U != (transfer->dataSize & 0x1U)) && (handle->bitsPerFrame > 8U))
|
|
{
|
|
handle->state = (uint8_t)kDSPI_Idle;
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]);
|
|
|
|
/* Store transfer information */
|
|
handle->txData = transfer->txData;
|
|
handle->rxData = transfer->rxData;
|
|
handle->remainingSendByteCount = transfer->dataSize;
|
|
handle->remainingReceiveByteCount = transfer->dataSize;
|
|
handle->totalByteCount = transfer->dataSize;
|
|
|
|
uint32_t wordToSend = 0;
|
|
uint8_t dummyData = DSPI_GetDummyDataInstance(base);
|
|
uint8_t dataAlreadyFed = 0;
|
|
uint8_t dataFedMax = 2;
|
|
|
|
uint32_t rxAddr = DSPI_GetRxRegisterAddress(base);
|
|
uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base);
|
|
|
|
edma_transfer_config_t transferConfigA = {0};
|
|
edma_transfer_config_t transferConfigC = {0};
|
|
|
|
DSPI_StopTransfer(base);
|
|
|
|
DSPI_FlushFifo(base, true, true);
|
|
DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag);
|
|
|
|
DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
|
|
|
|
DSPI_StartTransfer(base);
|
|
|
|
/*if dspi has separate dma request , need not prepare data first .
|
|
else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to
|
|
slaveGetTxRegister if there is no fifo*/
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
/* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
|
|
* trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
|
|
*/
|
|
/* If bits/frame is greater than one byte */
|
|
if (handle->bitsPerFrame > 8U)
|
|
{
|
|
while ((uint32_t)kDSPI_TxFifoFillRequestFlag ==
|
|
(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag))
|
|
{
|
|
if (NULL != handle->txData)
|
|
{
|
|
wordToSend = *(handle->txData);
|
|
++handle->txData; /* Increment to next data byte */
|
|
|
|
wordToSend |= (unsigned)(*(handle->txData)) << 8U;
|
|
++handle->txData; /* Increment to next data byte */
|
|
}
|
|
else
|
|
{
|
|
wordToSend = ((uint32_t)dummyData << 8U) | dummyData;
|
|
}
|
|
handle->remainingSendByteCount -= 2U; /* decrement remainingSendByteCount by 2 */
|
|
base->PUSHR_SLAVE = wordToSend;
|
|
|
|
/* Try to clear the TFFF; if the TX FIFO is full this will clear */
|
|
DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag);
|
|
|
|
dataAlreadyFed += 2U;
|
|
|
|
/* Exit loop if send count is zero, else update local variables for next loop */
|
|
if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == (dataFedMax * 2U)))
|
|
{
|
|
break;
|
|
}
|
|
} /* End of TX FIFO fill while loop */
|
|
}
|
|
else /* Optimized for bits/frame less than or equal to one byte. */
|
|
{
|
|
while ((uint32_t)kDSPI_TxFifoFillRequestFlag ==
|
|
(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag))
|
|
{
|
|
if (NULL != handle->txData)
|
|
{
|
|
wordToSend = *(handle->txData);
|
|
/* Increment to next data word*/
|
|
++handle->txData;
|
|
}
|
|
else
|
|
{
|
|
wordToSend = dummyData;
|
|
}
|
|
|
|
base->PUSHR_SLAVE = wordToSend;
|
|
|
|
/* Try to clear the TFFF; if the TX FIFO is full this will clear */
|
|
DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag);
|
|
/* Decrement remainingSendByteCount*/
|
|
--handle->remainingSendByteCount;
|
|
|
|
dataAlreadyFed++;
|
|
|
|
/* Exit loop if send count is zero, else update local variables for next loop */
|
|
if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == dataFedMax))
|
|
{
|
|
break;
|
|
}
|
|
} /* End of TX FIFO fill while loop */
|
|
}
|
|
}
|
|
|
|
/***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
|
|
if (handle->remainingReceiveByteCount > 0U)
|
|
{
|
|
EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
|
|
|
|
transferConfigA.srcAddr = (uint32_t)rxAddr;
|
|
transferConfigA.srcOffset = 0;
|
|
|
|
if (NULL != handle->rxData)
|
|
{
|
|
transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]);
|
|
transferConfigA.destOffset = 1;
|
|
}
|
|
else
|
|
{
|
|
transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull);
|
|
transferConfigA.destOffset = 0;
|
|
}
|
|
|
|
transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes;
|
|
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes;
|
|
transferConfigA.minorLoopBytes = 1;
|
|
transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount;
|
|
}
|
|
else
|
|
{
|
|
transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes;
|
|
transferConfigA.minorLoopBytes = 2;
|
|
transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2U;
|
|
}
|
|
|
|
/* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
|
|
handle->nbytes = (uint8_t)(transferConfigA.minorLoopBytes);
|
|
|
|
EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
(const edma_transfer_config_t *)(uint32_t)&transferConfigA, NULL);
|
|
EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
(uint32_t)kEDMA_MajorInterruptEnable);
|
|
}
|
|
|
|
if (handle->remainingSendByteCount > 0U)
|
|
{
|
|
/***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/
|
|
EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel);
|
|
|
|
transferConfigC.destAddr = (uint32_t)txAddr;
|
|
transferConfigC.destOffset = 0;
|
|
|
|
if (NULL != handle->txData)
|
|
{
|
|
transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0]));
|
|
transferConfigC.srcOffset = 1;
|
|
}
|
|
else
|
|
{
|
|
transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull);
|
|
transferConfigC.srcOffset = 0;
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
handle->txBuffIfNull = dummyData;
|
|
}
|
|
else
|
|
{
|
|
handle->txBuffIfNull = ((uint32_t)dummyData << 8U) | dummyData;
|
|
}
|
|
}
|
|
|
|
transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes;
|
|
|
|
if (handle->bitsPerFrame <= 8U)
|
|
{
|
|
transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes;
|
|
transferConfigC.minorLoopBytes = 1;
|
|
transferConfigC.majorLoopCounts = handle->remainingSendByteCount;
|
|
}
|
|
else
|
|
{
|
|
transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes;
|
|
transferConfigC.minorLoopBytes = 2;
|
|
transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2U;
|
|
}
|
|
|
|
EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
|
|
(const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL);
|
|
|
|
EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
|
|
}
|
|
|
|
EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
|
|
|
|
/*Set channel priority*/
|
|
uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
|
|
uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel;
|
|
uint8_t t = 0;
|
|
|
|
if (channelPriorityLow > channelPriorityHigh)
|
|
{
|
|
t = channelPriorityLow;
|
|
channelPriorityLow = channelPriorityHigh;
|
|
channelPriorityHigh = t;
|
|
}
|
|
|
|
edma_channel_Preemption_config_t preemption_config_t;
|
|
preemption_config_t.enableChannelPreemption = true;
|
|
preemption_config_t.enablePreemptAbility = true;
|
|
preemption_config_t.channelPriority = channelPriorityLow;
|
|
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
|
|
}
|
|
|
|
/*Set the channel link.
|
|
For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C.
|
|
For DSPI instances with separate RX and TX DMA requests:
|
|
Rx DMA request -> channel_A
|
|
Tx DMA request -> channel_C */
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
if (handle->remainingSendByteCount > 0U)
|
|
{
|
|
EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel);
|
|
}
|
|
DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable);
|
|
}
|
|
else
|
|
{
|
|
DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
|
|
void *g_dspiEdmaPrivateHandle,
|
|
bool transferDone,
|
|
uint32_t tcds)
|
|
{
|
|
assert(NULL != edmaHandle);
|
|
assert(NULL != g_dspiEdmaPrivateHandle);
|
|
|
|
dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle;
|
|
|
|
dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
|
|
|
|
DSPI_DisableDMA((dspiEdmaPrivateHandle->base), (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
|
|
|
|
dspiEdmaPrivateHandle->handle->state = (uint8_t)kDSPI_Idle;
|
|
|
|
if (NULL != dspiEdmaPrivateHandle->handle->callback)
|
|
{
|
|
dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
|
|
kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief DSPI slave aborts a transfer which is using eDMA.
|
|
*
|
|
* This function aborts a transfer which is using eDMA.
|
|
*
|
|
* param base DSPI peripheral base address.
|
|
* param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
|
|
*/
|
|
void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle)
|
|
{
|
|
assert(NULL != handle);
|
|
|
|
DSPI_StopTransfer(base);
|
|
|
|
DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
|
|
|
|
EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle);
|
|
EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle);
|
|
|
|
handle->state = (uint8_t)kDSPI_Idle;
|
|
}
|
|
|
|
/*!
|
|
* brief Gets the slave eDMA transfer count.
|
|
*
|
|
* This function gets the slave eDMA transfer count.
|
|
*
|
|
* param base DSPI peripheral base address.
|
|
* param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
|
|
* param count A number of bytes transferred so far by the non-blocking transaction.
|
|
* return status of status_t.
|
|
*/
|
|
status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count)
|
|
{
|
|
assert(NULL != handle);
|
|
|
|
if (NULL == count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Catch when there is not an active transfer. */
|
|
if (handle->state != (uint8_t)kDSPI_Busy)
|
|
{
|
|
*count = 0;
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
size_t bytes;
|
|
|
|
bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base,
|
|
handle->edmaRxRegToRxDataHandle->channel);
|
|
|
|
*count = handle->totalByteCount - bytes;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|