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201 lines
9.5 KiB
201 lines
9.5 KiB
/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
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* and flash clock are in allowed range during clock mode switch.
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*
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* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
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*
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* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
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* internal reference clock(MCGIRCLK). Follow the steps to setup:
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*
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* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
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*
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* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
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* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
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* explicitly to setup MCGIRCLK.
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*
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* 3). Don't need to configure FLL explicitly, because if target mode is FLL
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* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
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* if the target mode is not FLL mode, the FLL is disabled.
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*
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* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
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* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
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* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
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*
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* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v11.0
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processor: MK22FN512xxx12
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package_id: MK22FN512VLH12
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mcu_data: ksdk2_0
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processor_version: 13.0.1
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_smc.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
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#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
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#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
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#define SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK 1U /*!< LPUART clock select: PLLFLLSEL output clock */
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#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
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#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
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* Description : Configure FLL external reference divider (FRDIV).
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* Param frdiv : The value to set FRDIV.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
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{
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MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
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}
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: Bus_clock.outFreq, value: 60 MHz}
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- {id: Core_clock.outFreq, value: 120 MHz}
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- {id: Flash_clock.outFreq, value: 24 MHz}
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- {id: FlexBus_clock.outFreq, value: 30 MHz}
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- {id: IRC48MCLK.outFreq, value: 48 MHz}
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- {id: LPO_clock.outFreq, value: 1 kHz}
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- {id: LPUARTCLK.outFreq, value: 48 MHz}
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- {id: MCGFFCLK.outFreq, value: 250 kHz}
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- {id: MCGIRCLK.outFreq, value: 2 MHz}
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- {id: PLLFLLCLK.outFreq, value: 48 MHz}
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- {id: System_clock.outFreq, value: 120 MHz}
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settings:
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- {id: MCGMode, value: PEE}
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- {id: powerMode, value: HSRUN}
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- {id: LPUARTClkConfig, value: 'yes'}
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- {id: MCG.FRDIV.scale, value: '32'}
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- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
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- {id: MCG.IREFS.sel, value: MCG.FRDIV}
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- {id: MCG.PLLS.sel, value: MCG.PLL}
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- {id: MCG.PRDIV.scale, value: '2'}
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- {id: MCG.VDIV.scale, value: '30'}
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- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
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- {id: MCG_C1_IREFSTEN_CFG, value: Enabled}
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- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
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- {id: MCG_C2_RANGE0_CFG, value: Very_high}
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- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
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- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLSEL}
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- {id: SIM.OUTDIV2.scale, value: '2'}
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- {id: SIM.OUTDIV3.scale, value: '4'}
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- {id: SIM.OUTDIV4.scale, value: '5'}
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- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
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sources:
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- {id: IRC48M.IRC48M.outFreq, value: 48 MHz}
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- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const mcg_config_t mcgConfig_BOARD_BootClockRUN =
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{
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.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
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.irclkEnableMode = kMCG_IrclkEnable | kMCG_IrclkEnableInStop,/* MCGIRCLK enabled as well as in STOP mode */
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.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
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.fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
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.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
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.drs = kMCG_DrsLow, /* Low frequency range */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
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.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
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.pll0Config =
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{
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.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
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.prdiv = 0x1U, /* PLL Reference divider: divided by 2 */
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.vdiv = 0x6U, /* VCO divider: multiplied by 30 */
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},
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};
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const sim_clock_config_t simConfig_BOARD_BootClockRUN =
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{
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.pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
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.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
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.clkdiv1 = 0x1340000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /5 */
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};
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const osc_config_t oscConfig_BOARD_BootClockRUN =
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{
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.freq = 8000000U, /* Oscillator frequency: 8000000Hz */
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.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
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.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
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.oscerConfig =
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{
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.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
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.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
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}
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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{
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/* Set HSRUN power mode */
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SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
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SMC_SetPowerModeHsrun(SMC);
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while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
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{
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}
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/* Set the system clock dividers in SIM to safe value. */
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CLOCK_SetSimSafeDivs();
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/* Initializes OSC0 according to board configuration. */
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CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
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CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
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/* Configure the Internal Reference clock (MCGIRCLK). */
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CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
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mcgConfig_BOARD_BootClockRUN.ircs,
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mcgConfig_BOARD_BootClockRUN.fcrdiv);
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/* Configure FLL external reference divider (FRDIV). */
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CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
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/* Set MCG to PEE mode. */
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CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
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kMCG_PllClkSelPll0,
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&mcgConfig_BOARD_BootClockRUN.pll0Config);
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/* Set the clock configuration in SIM module. */
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CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
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/* Set LPUART clock source. */
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CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK);
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}
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