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591 lines
20 KiB
591 lines
20 KiB
/*
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* Copyright 2017-2019, 2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_CLOCK_H_
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#define _FSL_CLOCK_H_
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#include "fsl_common.h"
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/*! @addtogroup clock */
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/*! @{ */
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/*! @file */
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/*******************************************************************************
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* Definitions
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*****************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief CLOCK driver version 2.3.3. */
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#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 3))
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/*@}*/
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/* Definition for delay API in clock driver, users can redefine it to the real application. */
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#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
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#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (15000000UL)
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#endif
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/*! @brief lower power oscilltor clock frequency.
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*
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* This variable is used to store the lower power oscillator frequency which is
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* set by CLOCK_InitLPOsc, and it is returned by CLOCK_GetLPOscFreq.
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*/
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extern volatile uint32_t g_LP_Osc_Freq;
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/*! @brief external clock frequency.
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*
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* This variable is used to store the external clock frequency which is include
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* external oscillator clock and external clk in clock frequency value, it is
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* set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
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* when external oscillator is used as external clock ,and it is returned by
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* CLOCK_GetExtClkFreq.
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*/
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extern volatile uint32_t g_Ext_Clk_Freq;
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/*! @brief external clock frequency.
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*
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* This variable is used to store the FRO osc clock frequency.
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*/
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extern volatile uint32_t g_Fro_Osc_Freq;
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/*! @brief FRO clock setting API address in ROM. */
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#define CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F001CD3U)
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/*! @brief FAIM base address*/
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#define CLOCK_FAIM_BASE (0x50010000U)
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/*! @brief Clock ip name array for ADC. */
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#define ADC_CLOCKS \
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{ \
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kCLOCK_Adc, \
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}
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/*! @brief Clock ip name array for ACMP. */
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#define ACMP_CLOCKS \
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{ \
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kCLOCK_Acmp, \
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}
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/*! @brief Clock ip name array for DAC. */
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#define DAC_CLOCKS \
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{ \
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kCLOCK_Dac, \
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}
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/*! @brief Clock ip name array for SWM. */
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#define SWM_CLOCKS \
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{ \
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kCLOCK_Swm, \
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}
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/*! @brief Clock ip name array for ROM. */
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#define ROM_CLOCKS \
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{ \
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kCLOCK_Rom, \
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}
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/*! @brief Clock ip name array for SRAM. */
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#define SRAM_CLOCKS \
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{ \
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kCLOCK_Ram0, \
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}
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/*! @brief Clock ip name array for IOCON. */
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#define IOCON_CLOCKS \
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{ \
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kCLOCK_Iocon, \
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}
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/*! @brief Clock ip name array for GPIO. */
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#define GPIO_CLOCKS \
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{ \
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kCLOCK_Gpio0, \
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}
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/*! @brief Clock ip name array for GPIO_INT. */
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#define GPIO_INT_CLOCKS \
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{ \
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kCLOCK_GpioInt, \
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}
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/*! @brief Clock ip name array for CRC. */
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#define CRC_CLOCKS \
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{ \
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kCLOCK_Crc, \
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}
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/*! @brief Clock ip name array for WWDT. */
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#define WWDT_CLOCKS \
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{ \
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kCLOCK_Wwdt, \
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}
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/*! @brief Clock ip name array for SCT0. */
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#define SCT_CLOCKS \
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{ \
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kCLOCK_Sct, \
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}
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/*! @brief Clock ip name array for I2C. */
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#define I2C_CLOCKS \
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{ \
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kCLOCK_I2c0, kCLOCK_I2c1, \
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}
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/*! @brief Clock ip name array for I2C. */
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#define USART_CLOCKS \
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{ \
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kCLOCK_Uart0, kCLOCK_Uart1, \
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}
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/*! @brief Clock ip name array for SPI. */
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#define SPI_CLOCKS \
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{ \
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kCLOCK_Spi0, \
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}
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/*! @brief Clock ip name array for CAPT. */
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#define CAPT_CLOCKS \
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{ \
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kCLOCK_Capt, \
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}
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/*! @brief Clock ip name array for CTIMER. */
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#define CTIMER_CLOCKS \
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{ \
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kCLOCK_Ctimer0, \
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}
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/*! @brief Clock ip name array for MRT. */
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#define MRT_CLOCKS \
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{ \
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kCLOCK_Mrt, \
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}
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/*! @brief Clock ip name array for WKT. */
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#define WKT_CLOCKS \
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{ \
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kCLOCK_Wkt, \
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}
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/*! @brief Clock ip name array for PLU. */
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#define PLU_CLOCKS \
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{ \
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kCLOCK_PLU, \
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}
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/*! @brief Internal used Clock definition only. */
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#define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
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#define CLK_GATE_GET_REG(x) (((uint32_t)(x) >> 8U) & 0xFFU)
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#define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
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/* clock mux register definition */
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#define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
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#define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
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#define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
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#define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
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#define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) (((uint32_t)(x) >> 8U) & 0xFFU)
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#define CLK_MAIN_CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
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/* clock divider register definition */
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#define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
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#define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
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/* watch dog oscillator definition */
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//#define CLK_WDT_OSC_DEFINE(freq, regValue) ((freq & 0xFFFFFFU) | ((regValue & 0xFFU) << 24U))
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//#define CLK_WDT_OSC_GET_FREQ(x) ((uint32_t)x & 0xFFFFFFU)
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//#define CLK_WDT_OSC_GET_REG(x) ((x >> 24U) & 0xFFU)
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/* Fractional clock register map */
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/* Fractional clock register map */
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#define CLK_FRG_DIV_REG_MAP(base) (*(base))
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#define CLK_FRG_MUL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 4U)))
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#define CLK_FRG_SEL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 8U)))
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/* register offset */
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#define SYS_AHB_CLK_CTRL0 (0U)
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#define SYS_AHB_CLK_CTRL1 (4U)
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/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
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typedef enum _clock_ip_name
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{
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kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
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kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 0U), /*!< Clock gate name: Sys. */
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kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 1U), /*!< Clock gate name: Rom. */
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kCLOCK_Ram0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 2U), /*!< Clock gate name: Ram0. */
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kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 4U), /*!< Clock gate name: Flash. */
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kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 5U), /*!< Clock gate name: I2c0. */
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kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 6U), /*!< Clock gate name: Gpio0. */
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kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 7U), /*!< Clock gate name: Swm. */
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kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 9U), /*!< Clock gate name: Wkt. */
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kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 10U), /*!< Clock gate name: Mrt. */
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kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 11U), /*!< Clock gate name: Spi0. */
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kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 13U), /*!< Clock gate name: Crc. */
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kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 14U), /*!< Clock gate name: Uart0. */
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kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 15U), /*!< Clock gate name: Uart1. */
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kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 17U), /*!< Clock gate name: Wwdt. */
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kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 18U), /*!< Clock gate name: Iocon. */
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kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 19U), /*!< Clock gate name: Acmp. */
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kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 21U), /*!< Clock gate name: I2c1. */
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kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 24U), /*!< Clock gate name: Adc. */
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kCLOCK_Ctimer0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 25U), /*!< Clock gate name: Ctimer0. */
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kCLOCK_Dac = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 27U), /*!< Clock gate name: Dac. */
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kCLOCK_GpioInt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 28U), /*!< Clock gate name: GpioInt. */
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kCLOCK_Capt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL1, 0U), /*!< Clock gate name: Capt. */
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kCLOCK_PLU = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL1, 5U), /*!< Clock gate name: PLU. */
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} clock_ip_name_t;
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/*! @brief Clock name used to get clock frequency. */
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typedef enum _clock_name
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{
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kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
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kCLOCK_MainClk, /*!< Main clock */
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kCLOCK_Fro, /*!< FRO18/24/30 */
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kCLOCK_FroDiv, /*!< FRO div clock */
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kCLOCK_ExtClk, /*!< External Clock */
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kCLOCK_LPOsc, /*!< Watchdog Oscillator */
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kCLOCK_Frg0, /*!< fractional rate0 */
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} clock_name_t;
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/*! @brief Clock Mux Switches
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*CLK_MUX_DEFINE(reg, mux)
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*reg is used to define the mux register
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*mux is used to define the mux value
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*
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*/
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typedef enum _clock_select
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{
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kCAPT_Clk_From_Fro = CLK_MUX_DEFINE(CAPTCLKSEL, 0U), /*!< Mux CAPT_Clk from Fro. */
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kCAPT_Clk_From_MainClk = CLK_MUX_DEFINE(CAPTCLKSEL, 1U), /*!< Mux CAPT_Clk from MainClk. */
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kCAPT_Clk_From_Fro_Div = CLK_MUX_DEFINE(CAPTCLKSEL, 3U), /*!< Mux CAPT_Clk from Fro_Div. */
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kCAPT_Clk_From_LPOsc = CLK_MUX_DEFINE(CAPTCLKSEL, 4U), /*!< Mux CAPT_Clk from LPOsc. */
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kADC_Clk_From_Fro = CLK_MUX_DEFINE(ADCCLKSEL, 0U), /*!< Mux ADC_Clk from Fro. */
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kADC_Clk_From_Extclk = CLK_MUX_DEFINE(ADCCLKSEL, 1U), /*!< Mux ADC_Clk from Extclk. */
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kUART0_Clk_From_Fro = CLK_MUX_DEFINE(UART0CLKSEL, 0U), /*!< Mux UART0_Clk from Fro. */
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kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(UART0CLKSEL, 1U), /*!< Mux UART0_Clk from MainClk. */
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kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(UART0CLKSEL, 2U), /*!< Mux UART0_Clk from Frg0Clk. */
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kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(UART0CLKSEL, 4U), /*!< Mux UART0_Clk from Fro_Div. */
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kUART1_Clk_From_Fro = CLK_MUX_DEFINE(UART1CLKSEL, 0U), /*!< Mux UART1_Clk from Fro. */
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kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(UART1CLKSEL, 1U), /*!< Mux UART1_Clk from MainClk. */
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kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(UART1CLKSEL, 2U), /*!< Mux UART1_Clk from Frg0Clk. */
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kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(UART1CLKSEL, 4U), /*!< Mux UART1_Clk from Fro_Div. */
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kI2C0_Clk_From_Fro = CLK_MUX_DEFINE(I2C0CLKSEL, 0U), /*!< Mux I2C0_Clk from Fro. */
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kI2C0_Clk_From_MainClk = CLK_MUX_DEFINE(I2C0CLKSEL, 1U), /*!< Mux I2C0_Clk from MainClk. */
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kI2C0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(I2C0CLKSEL, 2U), /*!< Mux I2C0_Clk from Frg0Clk. */
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kI2C0_Clk_From_Fro_Div = CLK_MUX_DEFINE(I2C0CLKSEL, 4U), /*!< Mux I2C0_Clk from Fro_Div. */
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kI2C1_Clk_From_Fro = CLK_MUX_DEFINE(I2C1CLKSEL, 0U), /*!< Mux I2C1_Clk from Fro. */
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kI2C1_Clk_From_MainClk = CLK_MUX_DEFINE(I2C1CLKSEL, 1U), /*!< Mux I2C1_Clk from MainClk. */
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kI2C1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(I2C1CLKSEL, 2U), /*!< Mux I2C1_Clk from Frg0Clk. */
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kI2C1_Clk_From_Fro_Div = CLK_MUX_DEFINE(I2C1CLKSEL, 4U), /*!< Mux I2C1_Clk from Fro_Div. */
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kSPI0_Clk_From_Fro = CLK_MUX_DEFINE(SPI0CLKSEL, 0U), /*!< Mux SPI0_Clk from Fro. */
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kSPI0_Clk_From_MainClk = CLK_MUX_DEFINE(SPI0CLKSEL, 1U), /*!< Mux SPI0_Clk from MainClk. */
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kSPI0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(SPI0CLKSEL, 2U), /*!< Mux SPI0_Clk from Frg0Clk. */
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kSPI0_Clk_From_Fro_Div = CLK_MUX_DEFINE(SPI0CLKSEL, 4U), /*!< Mux SPI0_Clk from Fro_Div. */
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kFRG0_Clk_From_Fro = CLK_MUX_DEFINE(FRG[0].FRGCLKSEL, 0U), /*!< Mux FRG0_Clk from Fro. */
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kFRG0_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[0].FRGCLKSEL, 1U), /*!< Mux FRG0_Clk from MainClk. */
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kCLKOUT_From_Fro = CLK_MUX_DEFINE(CLKOUTSEL, 0U), /*!< Mux CLKOUT from Fro. */
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kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 1U), /*!< Mux CLKOUT from MainClk. */
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kCLKOUT_From_ExtClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U), /*!< Mux CLKOUT from ExtClk. */
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kCLKOUT_From_Lposc = CLK_MUX_DEFINE(CLKOUTSEL, 4U), /*!< Mux CLKOUT from Lposc. */
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} clock_select_t;
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/*! @brief Clock divider
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*/
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typedef enum _clock_divider
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{
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kCLOCK_DivAhbClk = CLK_DIV_DEFINE(SYSAHBCLKDIV), /*!< Ahb Clock Divider. */
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kCLOCK_DivAdcClk = CLK_DIV_DEFINE(ADCCLKDIV), /*!< Adc Clock Divider. */
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kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV), /*!< Clk Out Divider. */
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} clock_divider_t;
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//
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// typedef enum _clock_wdt_analog_freq
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//{
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// kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U),
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// kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U),
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// kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u),
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// kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U),
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// kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U),
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// kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U),
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// kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U),
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// kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U),
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// kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U),
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// kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U),
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// kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U),
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// kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U),
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// kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U),
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// kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U),
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// kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U),
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// kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U),
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//} clock_wdt_analog_freq_t;
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/*! @brief fro output frequency source definition */
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// typedef enum _clock_fro_src
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//{
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// kCLOCK_FroSrcLpwrBootValue = 0U,
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// kCLOCK_FroSrcFroOsc = 1U << SYSCON_FROOSCCTRL_DIRECT_SHIFT,
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//} clock_fro_src_t;
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/*! @brief fro oscillator output frequency value definition */
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typedef enum _clock_fro_osc_freq
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{
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kCLOCK_FroOscOut18M = 18000U, /*!< FRO oscillator output 18M */
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kCLOCK_FroOscOut24M = 24000U, /*!< FRO oscillator output 24M */
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kCLOCK_FroOscOut30M = 30000U, /*!< FRO oscillator output 30M */
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} clock_fro_osc_freq_t;
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/*! @brief PLL clock definition.*/
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// typedef enum _clock_sys_pll_src
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//{
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// kCLOCK_SysPllSrcFRO = 0U,
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// kCLOCK_SysPllSrcExtClk = 1U,
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// kCLOCK_SysPllSrcWdtOsc = 2U,
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// kCLOCK_SysPllSrcFroDiv = 3U,
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//} clock_sys_pll_src;
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/*!< Main clock source definition */
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typedef enum _clock_main_clk_src
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{
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kCLOCK_MainClkSrcFro = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
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kCLOCK_MainClkSrcExtClk = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from Ext clock */
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kCLOCK_MainClkSrcLPOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from lower power oscillator */
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kCLOCK_MainClkSrcFroDiv = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from FRO Div */
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// kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(0U, 1U),
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} clock_main_clk_src_t;
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/*! @brief PLL configuration structure */
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// typedef struct _clock_sys_pll
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//{
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// uint32_t targetFreq;
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// clock_sys_pll_src src;
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//} clock_sys_pll_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/*!
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* @name Clock gate, mux, and divider.
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* @{
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*/
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/*
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*! @brief enable ip clock.
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*
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* @param clk clock ip definition.
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*/
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static inline void CLOCK_EnableClock(clock_ip_name_t clk)
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{
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*(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) |=
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1UL << CLK_GATE_GET_BITS_SHIFT(clk);
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}
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/*
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*!@brief disable ip clock.
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*
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* @param clk clock ip definition.
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*/
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static inline void CLOCK_DisableClock(clock_ip_name_t clk)
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{
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*(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) &=
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~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
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}
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/*
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*! @brief Configure the clock selection muxes.
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* @param mux : Clock to be configured.
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* @return Nothing
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*/
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static inline void CLOCK_Select(clock_select_t sel)
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{
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*(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
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}
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/*
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*! @brief Setup peripheral clock dividers.
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* @param name : Clock divider name
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* @param value: Value to be divided
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* @return Nothing
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*/
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static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
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{
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CLK_DIV_GET_REG(name) = value & 0xFFU;
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}
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/*
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*! @brief Get peripheral clock dividers.
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* @param name : Clock divider name
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* @return clock divider value
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*/
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static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
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{
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return CLK_DIV_GET_REG(name) & 0xFFU;
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}
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/*
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*! @brief Setup Core clock dividers.
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* Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
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* @param value: Value to be divided
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* @return Nothing
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*/
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static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
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{
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assert(value != 0U);
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SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
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}
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/*! @brief Set main clock reference source.
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* @param src Reference clock_main_clk_src_t to set the main clock source.
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*/
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void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
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/*
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*! @brief Set Fractional generator multiplier value.
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* @param base: Fractional generator register address
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* @param mul : FRG multiplier value.
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* @return Nothing
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*/
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static inline void CLOCK_SetFRGClkMul(uint32_t *base, uint32_t mul)
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{
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CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK;
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CLK_FRG_MUL_REG_MAP(base) = SYSCON_FRG_FRGMULT_MULT(mul);
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}
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/*! @brief Set FRO clock source
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* @param src, please reference _clock_fro_src definition.
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*
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*/
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// void CLOCK_SetFroOutClkSrc(clock_fro_src_t src);
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/* @} */
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/*!
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* @name Get frequency
|
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* @{
|
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*/
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/*! @brief Return Frequency of FRG0 Clock.
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* @return Frequency of FRG0 Clock.
|
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*/
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uint32_t CLOCK_GetFRG0ClkFreq(void);
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|
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/*! @brief Return Frequency of Main Clock.
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|
* @return Frequency of Main Clock.
|
|
*/
|
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uint32_t CLOCK_GetMainClkFreq(void);
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/*! @brief Return Frequency of FRO.
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* @return Frequency of FRO.
|
|
*/
|
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uint32_t CLOCK_GetFroFreq(void);
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|
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/*! @brief Return Frequency of core.
|
|
* @return Frequency of core.
|
|
*/
|
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static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
|
|
{
|
|
return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
|
|
}
|
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|
|
/*! @brief Return Frequency of ClockOut
|
|
* @return Frequency of ClockOut
|
|
*/
|
|
uint32_t CLOCK_GetClockOutClkFreq(void);
|
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|
|
/*! @brief Get UART0 frequency
|
|
* @retval UART0 frequency value.
|
|
*/
|
|
uint32_t CLOCK_GetUart0ClkFreq(void);
|
|
|
|
/*! @brief Get UART1 frequency
|
|
* @retval UART1 frequency value.
|
|
*/
|
|
uint32_t CLOCK_GetUart1ClkFreq(void);
|
|
|
|
/*! @brief Return Frequency of selected clock
|
|
* @return Frequency of selected clock
|
|
*/
|
|
uint32_t CLOCK_GetFreq(clock_name_t clockName);
|
|
|
|
/*! @brief Get watch dog OSC frequency
|
|
* @retval watch dog OSC frequency value.
|
|
*/
|
|
static inline uint32_t CLOCK_GetLPOscFreq(void)
|
|
{
|
|
return g_LP_Osc_Freq;
|
|
}
|
|
|
|
/*! @brief Get external clock frequency
|
|
* @retval external clock frequency value.
|
|
*/
|
|
static inline uint32_t CLOCK_GetExtClkFreq(void)
|
|
{
|
|
return g_Ext_Clk_Freq;
|
|
}
|
|
/* @} */
|
|
|
|
/*!
|
|
* @name PLL operations
|
|
* @{
|
|
*/
|
|
|
|
/*! @brief System PLL initialize.
|
|
* @param config System PLL configurations.
|
|
*/
|
|
// void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
|
|
|
|
/* @} */
|
|
|
|
/*!
|
|
* @name Fractional clock operations
|
|
* @{
|
|
*/
|
|
|
|
/*! @brief Set FRG0 output frequency.
|
|
* @param freq target output frequency,freq < input and (input / freq) < 2 should be satisfy.
|
|
* @retval true - successfully, false - input argument is invalid.
|
|
*
|
|
*/
|
|
bool CLOCK_SetFRG0ClkFreq(uint32_t freq);
|
|
|
|
/* @} */
|
|
|
|
/*!
|
|
* @name External/internal oscillator clock operations
|
|
* @{
|
|
*/
|
|
|
|
/*! @brief Init external CLK IN, select the CLKIN as the external clock source.
|
|
* @param clkInFreq external clock in frequency.
|
|
*/
|
|
void CLOCK_InitExtClkin(uint32_t clkInFreq);
|
|
|
|
/*! @brief Deinit watch dog OSC */
|
|
static inline void CLOCK_DeinitLpOsc(void)
|
|
{
|
|
SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_LPOSC_PD_MASK;
|
|
}
|
|
|
|
// void CLOCK_InitSysOsc(uint32_t oscFreq);
|
|
|
|
// static inline void CLOCK_DeinitSysOsc(void)
|
|
//{
|
|
//
|
|
// SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
|
|
//}
|
|
|
|
// void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
|
|
|
|
// static inline void CLOCK_DeinitWdtOsc(void)
|
|
//{
|
|
// SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_LPOSC_PD_MASK;
|
|
//}
|
|
|
|
/*! @brief Set FRO oscillator output frequency.
|
|
* Initialize the FRO clock to given frequency (18, 24 or 30 MHz).
|
|
* @param freq Please refer to definition of clock_fro_osc_freq_t, frequency must be one of 18000, 24000 or 30000 KHz.
|
|
*
|
|
*/
|
|
void CLOCK_SetFroOscFreq(clock_fro_osc_freq_t freq);
|
|
|
|
/* @} */
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif /* __cplusplus */
|
|
|
|
/*! @} */
|
|
|
|
#endif /* _FSL_CLOCK_H_ */
|
|
|