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214 lines
6.7 KiB
214 lines
6.7 KiB
------------------------------------------------------------------------------
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-- --
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-- Copyright (C) 2015, AdaCore --
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-- --
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-- Redistribution and use in source and binary forms, with or without --
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-- modification, are permitted provided that the following conditions are --
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-- met: --
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-- 1. Redistributions of source code must retain the above copyright --
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-- notice, this list of conditions and the following disclaimer. --
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-- 2. Redistributions in binary form must reproduce the above copyright --
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-- notice, this list of conditions and the following disclaimer in --
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-- the documentation and/or other materials provided with the --
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-- distribution. --
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-- 3. Neither the name of the copyright holder nor the names of its --
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-- contributors may be used to endorse or promote products derived --
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-- from this software without specific prior written permission. --
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-- --
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS --
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT --
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR --
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-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT --
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-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, --
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT --
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-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, --
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-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY --
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-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE --
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-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --
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-- --
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------------------------------------------------------------------------------
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with System; use System;
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package STM32.Eth is
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procedure Initialize_RMII;
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-- Initialize the driver using RMII configuration.
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procedure Read_MMI (Reg : UInt5; Val : out UInt16);
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-- Read an MMI register.
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procedure Init_Mac;
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-- Initialize MAC layer.
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procedure Start_Rx;
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procedure Wait_Packet;
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type TDES0_Type is record
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Own : Bit;
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Ic : Bit;
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Ls : Bit;
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Fs : Bit;
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Dc : Bit;
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Dp : Bit;
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Ttse : Bit;
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Reserved_1 : Bit;
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Cic : UInt2;
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Ter : Bit;
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Tch : Bit;
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Reserved_2 : UInt2;
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Ttss : Bit;
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Ihe : Bit;
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Es : Bit;
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Jt : Bit;
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Ff : Bit;
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Ipe : Bit;
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Lca : Bit;
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Nc : Bit;
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Lco : Bit;
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Ec : Bit;
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Vf : Bit;
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Cc : UInt4;
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Ed : Bit;
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Uf : Bit;
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Db : Bit;
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end record;
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for TDES0_Type use record
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Own at 0 range 31 .. 31;
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Ic at 0 range 30 .. 30;
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Ls at 0 range 29 .. 29;
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Fs at 0 range 28 .. 28;
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Dc at 0 range 27 .. 27;
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Dp at 0 range 26 .. 26;
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Ttse at 0 range 25 .. 25;
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Reserved_1 at 0 range 24 .. 24;
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Cic at 0 range 22 .. 23;
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Ter at 0 range 21 .. 21;
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Tch at 0 range 20 .. 20;
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Reserved_2 at 0 range 18 .. 19;
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Ttss at 0 range 17 .. 17;
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Ihe at 0 range 16 .. 16;
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Es at 0 range 15 .. 15;
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Jt at 0 range 14 .. 14;
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Ff at 0 range 13 .. 13;
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Ipe at 0 range 12 .. 12;
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Lca at 0 range 11 .. 11;
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Nc at 0 range 10 .. 10;
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Lco at 0 range 9 .. 9;
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Ec at 0 range 8 .. 8;
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Vf at 0 range 7 .. 7;
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Cc at 0 range 3 .. 6;
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Ed at 0 range 2 .. 2;
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Uf at 0 range 1 .. 1;
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Db at 0 range 0 .. 0;
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end record;
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type TDES1_Type is record
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Tbs1 : UInt13;
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Reserved_13_15 : UInt3;
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Tbs2 : UInt13;
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Reserved_29_31 : UInt3;
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end record;
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for TDES1_Type use record
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Tbs1 at 0 range 0 .. 12;
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Reserved_13_15 at 0 range 13 .. 15;
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Tbs2 at 0 range 16 .. 28;
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Reserved_29_31 at 0 range 29 .. 31;
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end record;
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type Tx_Desc_Type is record
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Tdes0 : TDES0_Type;
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Tdes1 : TDES1_Type;
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Tdes2 : Address;
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Tdes3 : Address;
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end record;
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for Tx_Desc_Type use record
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Tdes0 at 0 range 0 .. 31;
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Tdes1 at 4 range 0 .. 31;
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Tdes2 at 8 range 0 .. 31;
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Tdes3 at 12 range 0 .. 31;
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end record;
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type Rdes0_Type is record
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Pce_Esa : Bit;
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Ce : Bit;
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Dre : Bit;
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Re : Bit;
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Rwt : Bit;
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Ft : Bit;
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Lco : Bit;
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Iphce : Bit;
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Ls : Bit;
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Fs : Bit;
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Vlan : Bit;
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Oe : Bit;
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Le : Bit;
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Saf : Bit;
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De : Bit;
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Es : Bit;
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Fl : UInt14;
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Afm : Bit;
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Own : Bit;
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end record;
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for Rdes0_Type use record
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Pce_Esa at 0 range 0 .. 0;
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Ce at 0 range 1 .. 1;
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Dre at 0 range 2 .. 2;
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Re at 0 range 3 .. 3;
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Rwt at 0 range 4 .. 4;
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Ft at 0 range 5 .. 5;
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Lco at 0 range 6 .. 6;
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Iphce at 0 range 7 .. 7;
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Ls at 0 range 8 .. 8;
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Fs at 0 range 9 .. 9;
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Vlan at 0 range 10 .. 10;
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Oe at 0 range 11 .. 11;
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Le at 0 range 12 .. 12;
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Saf at 0 range 13 .. 13;
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De at 0 range 14 .. 14;
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Es at 0 range 15 .. 15;
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Fl at 0 range 16 .. 29;
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Afm at 0 range 30 .. 30;
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Own at 0 range 31 .. 31;
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end record;
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type Rdes1_Type is record
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Rbs : UInt13;
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Reserved_13 : Bit;
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Rch : Bit;
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Rer : Bit;
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Rbs2 : UInt13;
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Reserved_29_30 : UInt2;
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Dic : Bit;
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end record;
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for Rdes1_Type use record
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Rbs at 0 range 0 .. 12;
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Reserved_13 at 0 range 13 .. 13;
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Rch at 0 range 14 .. 14;
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Rer at 0 range 15 .. 15;
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Rbs2 at 0 range 16 .. 28;
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Reserved_29_30 at 0 range 29 .. 30;
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Dic at 0 range 31 .. 31;
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end record;
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type Rx_Desc_Type is record
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Rdes0 : Rdes0_Type;
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Rdes1 : Rdes1_Type;
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Rdes2 : UInt32;
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Rdes3 : UInt32;
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end record;
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for Rx_Desc_Type use record
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Rdes0 at 0 range 0 .. 31;
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Rdes1 at 4 range 0 .. 31;
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Rdes2 at 8 range 0 .. 31;
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Rdes3 at 12 range 0 .. 31;
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end record;
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end STM32.Eth;
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